Design a $32-$bit ALU in Verilog with OR$,$ AND, NOR, ADD, SUB, and SLT logic as shown in the figure based on the given

models.

a$)$ Write your Verilog program for the $32-$bit ALU

b$)$ Discuss what type of Verilog models $($e$.$g$.$ Structural, Dataflow, hierarchical, etc.$)$ you have used and why. Also

show your comments for all the parameters such as input and output ports, connections, instances of other

lower$-$level modules, etc.

c$)$ Write a testbench for the $32$ bit ALU. In the case of random ALUcontrol, use only five control signals that can be

tested