Design a 3 bit ALU that receives the following inputs: CLK (bit), A (unsigned, 3 bits), B (unsigned, 3 bits), S (unsigned, 2 bits); and has the following outputs: seg (unsigned, 7 bits, active low), digit! (bit, active low), digitO (bit, active low). The circuit should display the result of the arithmetic or logical operation performed on the A and B inputs as selected by the S inputs. The result will be displayed on the two 7-segment displays called displayl and displavO. Displayl is turned on when digit! = 0, and display!) is turned on when digitO = 0. The displays receive the variable seg as input. Operations based on SI and SO are: The result of the addition and multiplication operations can result in two digit (decimal) numbers. However, there are only 7 outputs available which are connected to both displays. Therefore, implement a finite state machine which toggles back and forth between displaying digit 1 and digit 0 at a rate of 100Hz. Specifically, in one state digit 1=1 and digit0=0, and seg is assigned the value for digit 0. Then 10ms later the state changes to 1 in which digit 1=0 and digit0=l, and seg contains the value of digit 1. Assume Tcik = 50MHz. Please type your solution.