Design a 3-bit counter with a RESET line. When RESET is 0, it will count in the sequence 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 0, 1.. When RESET is 1, the counter will reset to 0 from any state. Take advantage of the unused count values 6 and 7 as dont cares in the design of the combinational logic. Show the following steps: specification, state transition diagram, state table, truth table, minimized functions from the truth table, and a block diagram showing the required number of D flip flops and input and output lines. You do not need to show the implementation of the combinational circuit.