Design a $4-$bit Full Adder using Verilog logical operators. Below, you see the block diagram for a $4-$bit Full Adder.

This is the circuit schematic for a $4-$bit Full Adder. Blue lines inside the box are not connected to any input or output ports. We need to define them in the code as a SIGNAL.

Define signals, complete the code and run the simulation. Write a testbench for your design and run the tests below.

$\backslash$table$[[$Test$1($Run for $20$ns$)$:$,A=0110,,B=0100,,$Cin$={?}^{\text{'}}{0}^{\text{'}}$

due to chegg not allowing me to upload mutiple picture, i upload it in a long picture, please use vivado to write me the code and a testbench, notice please only keep it in $2$ files,$($ex$.$ fulladder.v and testbench.v$)$