Design a 4-bit counter using Verilog that has the following requirements:

It can count up or down based on input enable_cnt_up and enable_cnt_dn.

The counter can be passed a new preset value by asserting new_cntr_preset high for one clock. The new_cntr_preset_value is stored and used as the starting value when counting down or as terminal value when counting up.

When enable_cnt_up or enable_cnt_dn is true, the counter keeps counting. At every rising edge of enable_cnt_up/enable_cnt_dn signal, the counter gets loaded with the initial value (max value when counting down and zero when counting up). As long as enable_cnt_up or enable_cnt_dn is true, it keeps counting unless pause_counting is asserted.

when pause_counting is asserted, the counter stops counting and retains the value.

when the counting reaches the end mark, it generates an output ctr_expired.

after counter expires, it auto loads to the preset value and starts counting again.

Give verilog code, testbench code, and waveforms of input and outputs.