Design a 64-bit adder in Verilog using a multi-level Carry Lookahead (CLA) strategy in two versions as below:

-Each CLA block adds 4 pairs of bits with one carryIn bit

-Each CLA block adds 8 pairs of bits with one carryIn bit

For each design version, include a design description and explain the calculation of total (gate) delay time for the entire addition. Assume that AND/OR/XOR gates can have any number of inputs. Also, compare both versions and write the advantages and disadvantages of each design.