Design a behavioral description of an instruction fetch unit to satisfy the requirements below (I need help with the Jmp, Jaddr, and Mdata design entities)

Address This 32-bit output provides an address value to the memory system. This should be the address of the instruction to be fetched.

Inst This 32-bit output provides the instruction that was received from the memory system.

Read This 1-bit control output is set to 1 and sent to the memory system to indicate that a memory read is requested. This control should be set to 0 to indicate that no memory read is requested.

Clock This design entity should include a program counter that is incremented (by 4) to fetch the next sequential instruction. The program counter should be loaded with a new value when there is a rising edge on this 1-bit clock input. The value in the program counter is sent to the memory through the Address output to provide the address in memory where the next instruction resides

Jmp This 1-bit control input indicates that a new value should be loaded into the program counter (PC) rather than loading the PC with the next sequential instruction address. When Jmp is 1 the PC should be loaded from the Jaddr input on the next rising edge of Clock. Jaddr This 32-bit input provides a jump address that will be loaded onto the PC if the Jmp control is asserted.

Reset This 1-bit control input is used to reset the PC to all zeros. If Reset = 1, then PC should be set to zero on the next rising edge of the clock.

Mdata This 32-bit input provides the data returned from the memory system.

Delay This 1-bit status input indicates that the memory system is delayed.

The purpose of this instruction fetch unit is to interact with the memory system to provide a steady stream of instructions through the Inst output. Asserting the Reset control sets the PC to zero on the next rising edge of the clock. This zero value from the PC is sent to the memory system through Address, and Read is asserted. The memory system then must either return the contents of the address through Mdata or the memory system must assert Delay. If the memory system returns an instruction through Mdata, then this fetch unit must place the instruction received from Mdata on the Inst output. All of this must occur before the next rising clock edge when the PC is incremented (by 4) to the address of the next sequential instruction.

If the Jmp control input is asserted, then the PC is loaded from the Jaddr input on the next rising clock edge rather than loading the PC with the address of the next sequential instruction. The memory system asserts Delay before the next rising clock edge to indicate that the memory system is not ready to provide a value on Mdata. If the memory system cannot provide an instruction, then the fetch unit must send the code for No Operation (NOP) on the Inst output. The special bit pattern for NOP is: 00000000 00000000 00000000 00010011

As long as the memory system continues to assert Delay, the fetch unit must keep the Address value unchanged with the address of the instruction. Eventually, the memory system will provide an instruction on Mdata and will de-assert Delay. When Delay is de-asserted, the instruction provided on Mdata should be sent to Inst and the PC should be loaded with the next address value.

The special NOP code should also be sent to Inst when either the Jmp control input or the Reset control input is asserted. If both Jmp and Reset are asserted at the same time, then the Reset is handled and the Jmp is ignored.

If the Jmp is asserted while the memory system has Delay asserted, then the Read control should be de-asserted. This will cancel the memory read request so that the Delay will be de-asserted.