Design a circuit that takes in a clock of 100 MHz and produces a clock signal with a period of 50 ns and duty cycle of 40%. The output should be free of glitches. You will be essentially designing a Clock Divider with a particular duty cycle requirement, which is essentially a counter. No need for a reset input.

a) Q3 5 pts: What are the inputs and outputs of a positive edge triggered D-type flip-flops? Draw and name them.

b) : Draw the bubble diagram. (The state machine can power up in any state. Therefore, unused states should transition to the designated reset state.)

c) First draw the circuit as a cloud of logic and specific flops, i.e., name the flops and explain the purpose of each. (Flop means positive edge triggered D-type flip-flop.)

d) 15 pts: Implement the TT using AND2 (i.e., 2-input AND gate), OR2, and INV gates. Draw a circuit schematic.

e)

Convert the design of the logic cloud to NAND2 gates. Draw a circuit schematic.