Design a datapath incorporating four registers R0, R1, R2 and R3 that is able to execute the following register transfers controlled by three mutually exclusive control signals Ca, Cb, Cc:

Ca: R1->R2; R1->R0

Cb: R0->R2; R2->R3

Cc: R1->R3; R3->R1

Implement the datapath using 1) Point-point connection using four 4:1 multiplexers and 2) bus connection. Draw the circuits diagram and derive the control sequences for the three control signals Ca, Cb and Cc, and describe the transfer operations. For the bus connection you can use one of the unused register as temporary register