design a finite state machine $($FSM$)$ to detect the sequence $00100$ in a bit stream. The output should be a single bit that goes high $(1)$ whenever the sequence has been detected. Note that the input $00100100$ should result in two detections.Note however, that it does not consider overlapping sequences. make sure you use the minimum states you can. this is i have done, can you do it in $4$ states?

Design a circuit to implement your state machine. Show the minimisation process and the final equations in your report.

Implement and simulate your design using Digital$/$Logisim to verify functionality. Log the simulation to a file or create a waveformcan you help me with these