Design a module that counts the number of $0\text{'}$s in an input word. The code should be parametrizable with an initial value of

word$-$size $=16.$ The word size should be a parameter that can be changed without updating anything else in the code, and yet

get no errors while compiling the code and obtaining correct functionality. The module should represent combinational logic

that would update the count whenever the input word changes.

Add any additional parameters you need and use any code style or loop $($for loop, while loop, or repeat$)$ you prefer.

Test the design using a testbench and verify that the design works for $16-$bit words as well as $8-$bit words. Indicate what

parameters had to be updated for each case.

Share the Verilog code, the testbench code, and the simulation results, and how you verified the correct functionality of the

code.