Design a Moore FSM that produces the following sequence repeatedly: 0, 1, 3, 5, 0. Single bit output y=1 only when 5 is reached. Use three D-FFs in your design. Name and assign states sequentially; e.g. S0 = 000, S1=001, S2=010, S3=011 etc. a) (8 pts) Draw the state diagram. b) (4 pts) Write the excitation table c) (12 pts) Write the K-maps for each of the next state bits d) ( 9pts) Implement the next state logic using a minimum number of gates e) (2 pts) Implement the single bit output y using a minimum number of gates