Design a Multiplier Algorithmic State Machine (ASM) circuit that is similar to the division circuit we saw last week. This circuit will have; - Two 8 bits registered data inputs, two 8 bits registered data outputs, - One clock signal input, - One "Start" input and one "Busy/Ready" registered output (0 when Ready, 1 when Busy). The registered inputs and outputs mean that the data will first be stored within an appropriate size register. The algorithm will compute the result by performing the below steps; - The ASM will wait for the Start signal to rise to logic 1 and keep the Busy/Ready signal low. - When the Start signal is asserted, the ASM will load A and B 8 bits data into respective registers and raise the Busy/Ready flag to logic 1. - Within a loop, the ASM will accumulate on two 8 bit registers, the content of A. The loop will run B times. The basics of the multiplication can be summarized as "adding A B times". - When the loop is exhausted, the ASM will wait until the Start signal is 0 and clears the Busy/Ready flag. - After the Start signal drops to the logic 0, the ASM will return to the initial state where it waits for the Start signal again. The smaller the value in B register, the faster the computation is. This is a context sensitive machine whose computation time depends on the input values. The design procedure will consist of: - Designing the ASM flowchart together with the Data Computation Machine, - Deriving the state diagram, - Designing the State Machine who controls the sequences of Data Computation Machine, - Establishing the control signals that connects Data Computation Machine and State Machine, - Drawing the schematic of the complete system