Design adders and analyze its time delay. (15%) 1) Design a full adder, write down the truth table, logic expressions, and draw its circuit. (5%) 2) Design a 4 bit-Binary Ripple Carry Adder using 4 full adders you designed and Draw the circuit using block diagram. Analyze the time delay of it only considering the delay of gates. Suppose the delay of one NAND, NOR, NOT gate is Tg, the delay of AND and OR gate is 2Tg, the delay of XOR and XNOR gate is 3T, and you do not need to consider the delay of wires. (5%) 3) Now consider an n bit-Binary Ripple Carry Adder like the following figure and the delay of one gate is still as described in 2). How long is the delay of such an adder? (5%) C B-1A-1 TI FAn-1 B A IT FA Sn-1 Bo Ao FAo S Figure 1: n-bit Binary Ripple Carry Adder So Co