Design an $32$ bit ALU in Verilog with OR$,$ AND, NOR, ADD, SUB,

SLT logic as shown in the figure based on the given models. Attach screen$-$shots of

outputs, answers to the questions, verilog code. Moreover, submit your code as

separate files so that the grader can test it$.$ Check the tutorial at the end.

a$.$ Write your verilog program for the $32$ bit ALU

b$.$ Discuss what type of Verilog models $($e$.$g$.$ Structural, Dataflow, hierarchical etc.$)$

you have used and why? Also show your comments for all the parameters such

as input and output ports, connections, instances of other lower level modules

etc.

c$.$ Write a testbench for the $32$ bit ALU. Use the tutorial $($at the end$)$ for writing your

testbench. In the case of random ALUcontrol, use only five control signals that

can be tested

d$.$ Compile and run your simulations in ModelSIm. Test whether your results are

correct.