Design an ALU that provides support for implementing the following instructions: AND, ORR, ADD, SUB, LDUR, STUR, and CBZ. All operations must have a delay of 20 before the output is available. Use non-blocking assignments as shown in the provided template: ALU.V Your ALU should implement the following operations (which are needed to support the instructions in the pre-lab) Operation ALU Control Line AND OR ADD SUB PassB 0001 0010 0110 0111 You should use the provided ALU code template ALU.v. You will need to extend it for your own purposes. The ALU module has the following interface: module ALU(BusW, Zero, BusA, BusB, ALUCtrl) Ports BusA, BusB, and busW are 64 bits wide. ALUCtrl is 4 bits wide, supporting up to 16 functions. Port Zero is a boolean variable that is 'true' (1) when BusW is 0, and 'false' (0) otherwise. Design an ALU that provides support for implementing the following instructions: AND, ORR, ADD, SUB, LDUR, STUR, and CBZ. All operations must have a delay of 20 before the output is available. Use non-blocking assignments as shown in the provided template: ALU.V Your ALU should implement the following operations (which are needed to support the instructions in the pre-lab) Operation ALU Control Line AND OR ADD SUB PassB 0001 0010 0110 0111 You should use the provided ALU code template ALU.v. You will need to extend it for your own purposes. The ALU module has the following interface: module ALU(BusW, Zero, BusA, BusB, ALUCtrl) Ports BusA, BusB, and busW are 64 bits wide. ALUCtrl is 4 bits wide, supporting up to 16 functions. Port Zero is a boolean variable that is 'true' (1) when BusW is 0, and 'false' (0) otherwise