Design some signal conditioning circuitry that accepts a common mode input to drive an Analogue to Digital Converter (ADC) that has a differential input. It should have pre-settable gains of X1 X2 X5 X10 and anti-aliasing filter allowing response up to 600 Hz. The ADC resolution is 12 bits over a 3V range. Along with a circuit description, construct a suitable circuit with a single ended or common mode input stage, a filter stage and differential output stage to drive the differential input of the analogue to digital converter. The input resistance to the signal conditioning circuit should be 600 k2. Include a 2nd order low pass filter with a response from DC to 600 Hz. For a second order low pass filter with breakpoint set to 600 Hz what is the residual signal amplitude at 6000 Hz with an input signal of 2.5V peak? What is the number of bits this residual signal equates to? What is the minimal sample rate for the ADC and for a same 2nd order filter and input? What is the residual signal amplitude at this frequency?