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Design this Hamming code in verilog. Create one module for the 3 - to - 8 decoder ( dec 3 to 8 ) and a
Design this Hamming code in verilog. Create one module for the to decoder decto and a top module hc that instantiates decto and add all the XOR gates. In the Hamming code design, you should use all three levels of modeling at least once: dataflow assign behavioral always and structural instantiation
Use the following testbench to run your simulation. Include the waveform.
module topmodule ;
reg clk;
always # clk ~clk; Create clock with period
initial probestart; Start the timing diagram
probeclk; Probe signal clk
A testbench
reg : in;
initial begin
the first valid cases, followed by invalid codes
p bbb p bbb p bbb
order: bbbpbpp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
# in b; bbbb ppp
$display Hello world! The current time is d ps $time;
# $finish; Quit the simulation
end
hc DUT inin; Submodules work too.
endmodule
module hcinput : in output : out, output noerror;
wire p p p;
wire : pos ppp;
wire : decout;
add your code here
probein; probepos; probenoerror; probeout;
endmodule
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