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Design this Hamming code in verilog. Create one module for the 3 - to - 8 decoder ( dec 3 to 8 ) and a

Design this Hamming code in verilog. Create one module for the 3-to-8 decoder (dec3to8) and a top module (hc7) that instantiates dec3to8 and add all the XOR gates. In the Hamming code design, you should use all three levels of modeling at least once: dataflow (assign), behavioral (always), and structural (instantiation).
Use the following testbench to run your simulation. Include the waveform.
module top_module ();
reg clk=0;
always #5 clk = ~clk; // Create clock with period=10
initial `probe_start; // Start the timing diagram
`probe(clk); // Probe signal "clk"
// A testbench
reg [7:1] in=0;
initial begin
//the first 16 valid cases, followed by 8 invalid codes
// p4= b7^b6^b5, p2= b7^b6^b3, p1= b7^b5^b3
// order: b7b6b5p4b3p2p1
#10 in <=7'b000_0000; // b7b6b5b3=0000=> p4p2p1=000
#10 in <=7'b000_0111; // b7b6b5b3=0001=> p4p2p1=011
#10 in <=7'b001_1001; // b7b6b5b3=0010=> p4p2p1=101
#10 in <=7'b001_1110; // b7b6b5b3=0011=> p4p2p1=110
#10 in <=7'b010_1010; // b7b6b5b3=0100=> p4p2p1=110
#10 in <=7'b010_1101; // b7b6b5b3=0101=> p4p2p1=101
#10 in <=7'b011_0011; // b7b6b5b3=0110=> p4p2p1=011
#10 in <=7'b011_0100; // b7b6b5b3=0111=> p4p2p1=000
#10 in <=7'b100_1011; // b7b6b5b3=1000=> p4p2p1=111
#10 in <=7'b100_1100; // b7b6b5b3=1001=> p4p2p1=100
#10 in <=7'b101_0010; // b7b6b5b3=1010=> p4p2p1=010
#10 in <=7'b101_0101; // b7b6b5b3=1011=> p4p2p1=001
#10 in <=7'b110_0001; // b7b6b5b3=1100=> p4p2p1=001
#10 in <=7'b110_0110; // b7b6b5b3=1101=> p4p2p1=010
#10 in <=7'b111_1000; // b7b6b5b3=1110=> p4p2p1=100
#10 in <=7'b111_1111; // b7b6b5b3=1111=> p4p2p1=111
#10 in <=7'b111_1110; // b7b6b5b3=1111=> p4p2p1=111
#10 in <=7'b111_1101; // b7b6b5b3=1111=> p4p2p1=111
#10 in <=7'b111_1011; // b7b6b5b3=1111=> p4p2p1=111
#10 in <=7'b111_0111; // b7b6b5b3=1111=> p4p2p1=111
#10 in <=7'b110_1111; // b7b6b5b3=1111=> p4p2p1=111
#10 in <=7'b101_1111; // b7b6b5b3=1111=> p4p2p1=111
#10 in <=7'b011_1111; // b7b6b5b3=1111=> p4p2p1=111
$display ("Hello world! The current time is (%0d ps)", $time);
#20 $finish; // Quit the simulation
end
hc7 DUT (.in(in)); // Sub-modules work too.
endmodule
module hc7(input [7:1] in, output [7:1] out, output no_error);
wire p4, p2, p1;
wire [2:0] pos ={p4,p2,p1};
wire [7:0] dec_out;
// add your code here
`probe(in); `probe(pos); `probe(no_error); `probe(out);
endmodule

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