Design using a combinational VHDL process a sign magnitude to two's complement converter using the given algorithm and hardware description. Use the following VHDL entity specifica- tion: library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned. all; entity converter is port ( sign mag : in std_logic_vector (3 downto 0); twos_comp out std_logic_vector (3 downto 0)); end;