Determine whether the following signal assignment is syntactically correct. if not, use the proper conversion function and type casting to correct the problem.

library ieee ; use ieee,std-logic-1164. a l l ;

use ieee .numeric-std. a l l ;

s i g n a l sl, s2, s3, 94, s5, s6, s7: std-logic-vector(3 Downtown 0); s i g n a l ul, u2, u3, u4, u5, u6, u7: unsigned(3 downto 0);

signal sg: signed(3 downto 0);

U1 <= 2#0001#; u2 <= u3 and u4;

U5 <=s1+1;

u6 <= u3 + u4 + 3;

u7 <= (others => '1');

s2 <= s3 + s4 -1;

s5<= (others => '1');

s6 <= u3 and u4;

sg<= u3-1;

s7<=not sg;

sl + 1; u3 -+ u4 + 3;

(others=>l>;