Develop testbench code (or truth table) for two 4-bit inputs.

GREECOOvou Schultz Mux2.v Schult 8 TD 02 203 1 Omodule Schultz_Lab4_Proce output reg y, input wire[3:0] DO, 01, input wire s); always @(S, DO, 01) Ebegin if (S==1'bo) y = DO; else if (s==l'b1) y = D1; else y = 1'bx; end Lendmodule