Digital IC Design - Q3
Instruction: Enter the answer in the units specified and correct to four decimal places. t=0 VDD Vpp/2 VG T. C > = = 2 Consider an NMOS transistor that is connected to a capacitor, charged to Vod, at t = 0. The NMOS transistor has a sub-threshold slope S = 90 mV/decade and has non-zero DIBL coefficient n = 0.01. The transistor has a threshold voltage Vin = 430 mV whose gate is connected to VG Vin = 180 mV. Let the time taken to discharge the VOD capacitor from VDD + be denoted by TDIBL If you were to use an otherwise identical NMOS transistor, except for DIBL being absent, the time taken to discharge VDD the capacitor from VDD + is TNO-DIBL = 43 ps, for the same gate voltage Vin. Given VDD 2.7 V, answer the following and express all delays in picoseconds. Vad For the case when DIBL is absent, the time (in ps) taken to discharge the capacitor to when the gate voltage is connected to Vin/2 is - 2 2 VDD when the gate voltage is For the case when DIBL is present, the time in ps) taken to discharge the capacitor to connected to Vin is VpD 2 For the case when DIBL is present, the time in ps) taken to discharge the capacitor to connected to Vin/2 is when the gate voltage is You may assume that effect of DIBL on threshold voltage of the transistor can be modelled accurately with a linear model and that the circuit is operating at 298K. Instruction: Enter the answer in the units specified and correct to four decimal places. t=0 VDD Vpp/2 VG T. C > = = 2 Consider an NMOS transistor that is connected to a capacitor, charged to Vod, at t = 0. The NMOS transistor has a sub-threshold slope S = 90 mV/decade and has non-zero DIBL coefficient n = 0.01. The transistor has a threshold voltage Vin = 430 mV whose gate is connected to VG Vin = 180 mV. Let the time taken to discharge the VOD capacitor from VDD + be denoted by TDIBL If you were to use an otherwise identical NMOS transistor, except for DIBL being absent, the time taken to discharge VDD the capacitor from VDD + is TNO-DIBL = 43 ps, for the same gate voltage Vin. Given VDD 2.7 V, answer the following and express all delays in picoseconds. Vad For the case when DIBL is absent, the time (in ps) taken to discharge the capacitor to when the gate voltage is connected to Vin/2 is - 2 2 VDD when the gate voltage is For the case when DIBL is present, the time in ps) taken to discharge the capacitor to connected to Vin is VpD 2 For the case when DIBL is present, the time in ps) taken to discharge the capacitor to connected to Vin/2 is when the gate voltage is You may assume that effect of DIBL on threshold voltage of the transistor can be modelled accurately with a linear model and that the circuit is operating at 298K
