Dr. Weiying Zhu MSU Denver, M&CS CS 2400-001/002: Computer Organization 2, Spring 2018 Homework 1 (100 points) Due Date': 10:00am 01/29/2018, Cutoff Deadline": 10:00am 02/01/2018 Late penalty will apply for past-due late submission "Submission will NOT be accepted after the cutoff deadline Submission: handwritten hardcopy at the beginning of the class (Email to wzhu1@msudenver.edu must be used for late submission and the submission time is the moment when the email arrives at the instructor's inbox.) PLEASE ORGANIZE YOUR WORK IN THE SEQUENCE GIVEN IN THE ASSIGNMENT!!! Problem A: On an ARM processor, assuming that [N-bil-0, [Z-bit] 0, [C-bil-1, [V-bit-1, predict whether each of the following branch instruction is going to make the flow of control branch to the instruction labeled by NEXT. (These instructions are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.) (a) BLS NEXT (b) BNE NEXT (c) BLE NEXT (d) BVC NEXT Problem B. On an ARMv7-M processor, assuming that [R1] = 0x01 0E0C2D, [R2] = 0xFDB97531, [R3)-0x0000000C, [N-bit-1, [Z-bit] 0, [C-bit] 0, [V-bit]-1, predict the 32-bit [RI], [N-bit], [Z-bit], and [C-bit] after an ARM instruction is executed in EACH case. (These instructions are NOT executed one after the other; instead, each instruction starts with the initial conditions given in the statement.) (a) MOVS RI, #0xFAB (b) MOVS RI, R2, ASR #3 (c) MVNS R1, #0x2FC (d) MVNS R1, R2, LSL R3 (e) MOVS R1, R2, RRX (f) RORS RI, R2, #5 (g) LSRS RI, R2, R3 (h) MVNS R1, R2