Draw a cache plz. Will rate according to correctness of the answer. Thanks in advance

Draw the diagram of an 64KB capacity, 4-way set-associative, write-back cache with 32- byte blocks. Your diagram must show (A) how the cache is accessed using a 32 bit address, (B) the logic that shows how hit/miss is determined, (C) all cache structures including data and metadata(i.e., tags, other bits), and (D) how a 32-bit word is returned to the processor in case of a hit. Draw the diagram of an 64KB capacity, 4-way set-associative, write-back cache with 32- byte blocks. Your diagram must show (A) how the cache is accessed using a 32 bit address, (B) the logic that shows how hit/miss is determined, (C) all cache structures including data and metadata(i.e., tags, other bits), and (D) how a 32-bit word is returned to the processor in case of a hit