Draw a digital system that is synthesized from the Verilog program module Top$\_$Q$3($En$,$ Ck$,$ a$,$ b$,$ c$,$ d$,$ e$,$ g$,$ h$,$ S$,$ Z$)$;

input En$,$ Ck$,$ a$,$ b$,$ c$,$ d$,$ e$,$ g$,$ S;

input $[1$:$0]h$;

output $Z$;

wire $i,j,l,m,n$;

reg $k$;

IP$\_$Core$1$ M$0(.$A$($a$),.$B$($b$),.$C$($c$),.$En$($En$),.$F$($i$))$;

IP$-$Core $2Ml(.A(d),.B(e),.F(j))$;

IP Core$3$ M$2(.$X$($k$),.$Y$($n$),.$F$($Z$))$;

always@$($posedge Ck$)$

if $($S$)ki$;

else $kj$;

and$(1,h[1],g)$;

and $(m,h[0],g)$;

or $($n$,1,$ m$)$;

endmodule