Draw a Finite State Machine diagram to describe a serial comparator with n-bit unsigned numbers x and y as inputs. The FSM takes two bits xi and yi as inputs at each clock cycle). Assume that the bits are fed in from most significant to least significant. As soon as an inequality shows up, the comparator outputs a10 if x has a larger value, an 01 if y has a larger value, and as long as all of the x bits have equaled the corresponding y bits, the comparator outputs 00.