Draw a logical circuit of a four$-$bit register transfer command using a $4$bit parallel adder. XT:RR$1+$R$2,$ X$\text{'}$T:RR$2+$R$3.$ i attach an example$\{$:$[\stackrel{}{x}{T}_1$:$R_{1}larr{R}_1+R_2],[x{T}_1$:$R_{1}larr{R}_1\frac{+}{b}ar(R{)}_2+1])=>$