Draw a Register File that will adopt the following interface: As long as the validation line, rd_e, is inactive, the rd_data output is in high impedance. When rd_e is active, rd_data will be channeled the contents of the selected register.

a) Implement the designed architecture, using the Verilog language. b) Write a testbench for the regfl_4 8 module, which generates entries according to the diagram below (Tclk = 100 ns):

module regfi_4x8 ( input clk, input rst_b , // asynchr input [7:0] wr_data, input [1:0] wr_addr, input (1:0] rd_addr input wr_e, input rd_e, output [7:0] rd_data ); clk rst_b wr_addr wr_data 2'ho 2'h2 2'h1 2'h3 2'ho 2'h1 2'h3 2'h2 2'h3 8'ha2 8'h2e 8'h98 8'h55 8'h20 8'hff 8'hc7 8'hb5 8'h91 wr_e 2'h3 2'h0 2'h1 2'h2 2'h3 2'ho 2'h1 2'h2 2'h3 rd_addr rde