Draw a schematic of the logic defined in the following Verilog code.

2. (59) Draw a schematic of the logic defined in the following Verilog code module exercise2 (input [3:01 a, output reg [1:0] y) always@ (*) if else else else else (a[0]) if(a[1]) if (a[2]) if (a[3]) 2,b11: 2"b10: 2"b01: 2"b00; - - - - endmodule