Draw the gate-level logic diagram for a 4-10-1 MUX, a circuit in which one of four data input lines are connected to its single output, depending on the state of its 8. two control lines. You have been constructing a circuit and discover that you need one additional AND gate, but all you have is a chip with 2-to-1 MUXs. Show how to connect a 2-to-1 MUX to serve as an AND gate. (Assume you have access to Ves and Ground, in addition to your logic inputs.) 9. DO Di A