Draw the interface diagram that connects enough amount of $2$Kx$8$ EPROMs to

an Intel $8086\text{'}$s global bus signals in minimum mode, A$0,...,.$A$19,$ and DO$,...,$D$15,$ and

IO$/$M$,$ RD$,$ WR$,$ BHE. The address range to be decoded is AE$000$h $-$ AFFFFh.

Use full address decoding!

The EPROMs have a CS active low pin for enable and a RD pin active low. Half of the

EPROMs should be implemented as the EVEN bank and the other half as the ODD bank.

$($Important: Your design should be capable of working for all the four scenarios discussed

in class $($byte transfer from even location, byte transfer from odd location, word transfer from

even location, word transfer from odd location$).$

a$)(5$pts$)$ DRAW A MEMORY MAP OF THE SYSTEM BELOW:Q$3)(20$ pts$)$ Draw the interface diagram that connects enough amount of $2Kx8$ EPROMs to

an Intel $8086\text{'}$s global bus signals in minimum mode, A$0,....$A$19,$ and D$0,..,$D$15,$ and

$I\frac{O}{\frac{?}{?}}$bar $(M)\frac{,}{b}ar(RD)\frac{,}{b}ar(WR),$BHE. The address range to be decoded is AE$000$h$-$AFFFFh.

Use full address decoding!

EPROMs should be implemented as the EVEN bank and the other half as the ODD bank.

$($Important: Your design should be capable of working for all the four scenarios discussed

in class $($byte transfer from even location, byte transfer from odd location, word transfer from

even location, word transfer from odd location$).$

a$)(5$pts$)$ DRAW A MEMORY MAP OF THE SYSTEM BELOW:

h b$)(15$pts$)$ DRAW THE SCHEMATIC of THIS CONNECTION including DECODER $+$

MEMORY INTERFACING. No need for Address Bus Demultiplexing, Address$/$Data

Buffers. Only show the signals$/$buses mentioned in the question.