Draw the logic diagram of the digital circuit specified by the following Verilog description:

module Circuit_A(F1, F2, F3, A0, A1, B0, B1);

output F1, F2, F3;

input A0, A1, B0, B1;

wire w1, w2, w3, w4, w5, w6, w7;

or G1(F1, w1, w2, w3);

nor G2(F2, F1, F3);

and G3(F3, w4, w5);

and G4(w1, w6, B1);

or G5(w2, w6, w7, B0);

and G6(w3, w7, B0, B1);

not G7(w6, A1);

not G8(w7, A0);

xor G9(w4, A1, B1);

xnor G10(w5, A0, B0);

endmodule