Draw the logic diagram of the digital circuit specified by the following Verilog description:

module Circuit_A(A, B, C, D, F);

input A, B, C, D;

output F;

wire w, x, y, z, a, d;

and G1(x, B, C, d);

and G2(y, a, C);

and G3(w, z, B);

or G4(z, y, A);

or G5(F, x, w);

not G6(a, A);

not G7(d, D);

endmodule