Draw the logic diagram of the simplified circuit specified by the following Verilog description

module Circuit_1 (A, B, C, F);

input A, B, C;

output F;

wire w1, w2,w3,w4,w5,w6;

not (w1, A);

not (w2, B);

not (w3, C);

and (w4, w1,B,C);

and (w5, A,w2,w3);

and (w6, A,w2,C);

or (F, w4,w5,w6);

endmodule