Edge Triggered JK Flip Flops and MUXs

You need to write a top level module which contains your JKFFs with synchronous and asynchronous RESETs. The top level model will have input signal J, K (as switches), RESET (as button), and CLOCK (port number V10 from the board) and 2 outputs from JKFFs as LEDs. Show simulations (using ISIM)

a) Be hierarchical. Your final design will have 3 level hierarchy. Top model => JKFFs => MUX + DFF.

b) Follow input/output specifications.

c) Use MUX + DFF approach to build your JKFF.

Steps

1. Build a positive edge triggered DFF.

2. Add a synchronous reset.

a. The reset signal should be attached to a button when you load JTAG.

b. To eliminate (sidestep) the issue of a noisy button, use a clock to the FF that is very slow, e.g. 1 Hz, and hold the button for more than a second. To do this, count up or down the main system clock. As an example, you could count from 1 to 40x 10**6 (i.e. the internal clock of FPGA is 40MhZ) and use the end marker as your 1 Hz clock. The reason you want that clock to be slow is that when you move the switches (step 4b), you can observe the JKFF output. We provided you a clock divider Verilog file (clk_divider.v). You need to understand the implementation of this file, and make changes to satisfy required clock (1 Hz)

module clk_divider(

input clk_in,

input rst,

output reg divided_clk

);

parameter toggle_value = 21'b111111111111111111111;

reg[20:0] cnt;

always@(posedge clk_in or posedge rst)

begin

if (rst==1) begin

cnt <= 0;

divided_clk <= 0;

end

else begin

if (cnt==toggle_value) begin

cnt <= 0;

divided_clk <= ~divided_clk;

end

else begin

cnt <= cnt +1;

divided_clk <= divided_clk;

end

end

end

endmodule

3. Using a separate piece of code: Add an asynchronous reset.

a. Copy and reuse your old code with some modifications.

4. Add a MUX in front of the DFF so that functionally you have a JKFF.

a. Use the DFF with synchronous reset and MUX to build a JKFF with synchronous reset.

b. Use the DFF with asynchronous reset and MUX to build a JKFF with asynchronous reset.

c. Assign J and K to switches when you load the development board.

5. Instantiate two versions of JKFFs with synchronous and asynchronous resets in your top module.

a. Two JKFF modules will share the same inputs J, K, reset, and clock.

b. The final outputs of top module will be the output Q_syn from JKFF with synchronous reset and Q_asyn from JKFF with asynchronous reset.

c. Assign Q_syn and Q_asyn to LEDs when you load program to the board.

d. When you implement your design on board, remember to use a clock divider (basically a large counter, see 2.b) to slow down the board clock.

For each of the steps, build a test bench that shows your modules work. There are few inputs, so test them exhaustively. Simulate all the modules, but only load the hardware for the JKFF with the low-speed clock. Simulate using a high-speed clock. If you load the program to the board and correctly slow down the clock frequency, you are expected to see when you push reset button, the LED of Q_asyn responds immediately while the other LED of Q_syn will have some delay.