eI Exam2 (2).pdf PracticeExam2 (2).pdf Exam2 (3).pdf ?HWT.pdf LTX ? ? ? ? ? file:///C/Users/adithiya/Downloads/HW7.pdf ? ?? 1 of 1 n the I-cache size is 32-k(B and the D-cache is 64-KB with miss rates of 0.93% and In a split LI cache o 9.7%, respectively. This memory structure has two additional cache levels: L2 and L3, 1,2 is 128KB with a miss rate of 5.4%. L3 is 512KB with a miss rate of 2.3%. Latencies are: L1 l cycle, L2 16 cycles, L3 48 cycles, and main memory-120 cycles. 13% and 62% of the instructions (in the benchmark program) are loads and stores. respectively. a) Please deternine te AMAT of the processor at uses this menory organization. b) Let us assume that a write buffer is used at LI level. Thus, when a cache miss (on a write operation) occurs the data is written to this buffer; this in turn requires a (1) cycle. Please determine the AMAT c Let us assume now that we add a mechanism that send the critical word first from L2 to Ll D-cache. Sending the critical word first helps to forward data to the CPU; this mechanism reduces the associated miss penalty by 2 cycles. Please determine the AMAT 11:52 AM Type here to search 4/20/2018 1 eI Exam2 (2).pdf PracticeExam2 (2).pdf Exam2 (3).pdf ?HWT.pdf LTX ? ? ? ? ? file:///C/Users/adithiya/Downloads/HW7.pdf ? ?? 1 of 1 n the I-cache size is 32-k(B and the D-cache is 64-KB with miss rates of 0.93% and In a split LI cache o 9.7%, respectively. This memory structure has two additional cache levels: L2 and L3, 1,2 is 128KB with a miss rate of 5.4%. L3 is 512KB with a miss rate of 2.3%. Latencies are: L1 l cycle, L2 16 cycles, L3 48 cycles, and main memory-120 cycles. 13% and 62% of the instructions (in the benchmark program) are loads and stores. respectively. a) Please deternine te AMAT of the processor at uses this menory organization. b) Let us assume that a write buffer is used at LI level. Thus, when a cache miss (on a write operation) occurs the data is written to this buffer; this in turn requires a (1) cycle. Please determine the AMAT c Let us assume now that we add a mechanism that send the critical word first from L2 to Ll D-cache. Sending the critical word first helps to forward data to the CPU; this mechanism reduces the associated miss penalty by 2 cycles. Please determine the AMAT 11:52 AM Type here to search 4/20/2018 1