EXECUTE the complete 5 stages pipeline MIPS 32 bits processor. To combine the Verilog code with the coding below. iPLEASE GIVE the RTL simulation and Waveform of the complete 5 stage pipeline MiPs 32 bit processor. iiSHOW THE STEPS to get waveform in Quartus Altera Prime or Eda playground.

Register Coding: module Register(D,clk,Q); input D; // Data input input clk; // clock input output reg Q; // output Q always @(negedge clk) begin Q <= D; end endmodule ALU coding: module alu( input [7:0] A,B, // ALU 8-bit Inputs input [3:0] ALU_Sel,// ALU Selection output [7:0] ALU_Out, // ALU 8-bit Output output CarryOut // Carry Out Flag ); reg [7:0] ALU_Result; wire [8:0] tmp; assign ALU_Out = ALU_Result; // ALU out assign tmp = {1'b0,A} + {1'b0,B}; assign CarryOut = tmp[8]; // Carryout flag always @(*) begin case(ALU_Sel) 4'b0000: // Addition ALU_Result = A + B ; 4'b0001: // Subtraction ALU_Result = A - B ; 4'b0010: // Multiplication ALU_Result = A * B; 4'b0011: // Division ALU_Result = A/B; 4'b0100: // Logical shift left ALU_Result = A<<1; 4'b0101: // Logical shift right ALU_Result = A>>1; 4'b0110: // Rotate left ALU_Result = {A[6:0],A[7]}; 4'b0111: // Rotate right ALU_Result = {A[0],A[7:1]}; 4'b1000: // Logical and ALU_Result = A & B; 4'b1001: // Logical or ALU_Result = A | B; 4'b1010: // Logical xor ALU_Result = A ^ B; 4'b1011: // Logical nor ALU_Result = ~(A | B); 4'b1100: // Logical nand ALU_Result = ~(A & B); 4'b1101: // Logical xnor ALU_Result = ~(A ^ B); 4'b1110: // Greater comparison ALU_Result = (A>B)?8'd1:8'd0 ; 4'b1111: // Equal comparison ALU_Result = (A==B)?8'd1:8'd0 ; default: ALU_Result = A + B ; endcase end endmodule Data Memory Unit Coding: module data_memory ( input wire [31:0] addr, // Memory Address input wire [31:0] write_data, // Memory Address Contents input wire memwrite, memread, input wire clk, // All synchronous elements, including memories, should have a clock signal output reg [31:0] read_data // Output of Memory Address Contents ); reg [31:0] MEMORY[0:255]; // 256 words of 32-bit memory integer i; initial begin read_data <= 0; for (i = 0; i < 256; i = i + 1) begin MEMORY[i] = i; end end always @(posedge clk) begin if (memwrite == 1'b1) begin MEMORY[addr] <= write_data; end if (memread == 1'b1) begin read_data <= MEMORY[addr]; end end endmodule Sign Extension Unit Coding: module Sign_ex (unextend,extended); input [15:0] unextend; output [31:0] extended; assign extended = {{16{unextend[15]}}, unextend}; endmodule Mux 2x1 Coding: module m21(D0, D1, S, Y); output Y; input D0, D1, S; assign Y=(S)?D1:D0; endmodule