Exercise 6. [20 Marks] Below is a sequence of references to 16-bit memory word ad- dresses. 1, 18, 14, 16, 2, 3, 17, 18, 14, 15, 20, 21 (a) Consider an initially empty, direct-mapped cache with 2-word cache lines and a capacity of 32 bytes. Using the sequence of address references above, determine if each address referenced results in a hit or a miss. If the reference results in a cache miss, say which type of cache miss (cold, conflict, capacity) You may use the table below to help answering this question, but for the purposes of marking, we do not care about the tag, index, or block offset. (b) Consider an initially empty, 2-way set associative cache with 2-word cache lines, a ca- pacity of 32 bytes, and an LRU (least recently used) eviction policy. Using the sequence of address references above, determine if each address referenced results in a hit or a miss. If the reference results in a cache miss, say which type of cache miss (cold, conflict, capacity) You may use the table below to help answering this question, but for the purposes of marking, we do not care about the tag, index, or block offset. Word Address Index Block Offset Hit/Miss Type of Miss Tag 18 14 16 3 17 18 14 15 20 21