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Explain the working of parallel IN/Serial OUT Shift Register with the help of circuit diagram? Show the states of the 4-bit register (SRG 4)

Explain the working of parallel IN/Serial OUT Shift Register with the help of circuit diagram? Show the states of the 4-bit register (SRG 4) for the data input and clock waveforms in the figure 1. The register initially contains all 1s. Data in CLK D >C SRG 4 Do QQ Q

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