Extend your design from Part V code below so that is uses all 7-segment displays on your DE-series board. Your circuit needs to display a three- or four-letter word, corresponding to Table 2, using blank characters for unused displays. Implement rotation of this word from right-to-left as indicated in Table 4 and Table 5. To do this, you will need to connect 6-to-1 multiplexers to each of six 7-segment display decoders for the DE10-Lite. Note that for the DE10-Lite you will need to use 3-bit codes for your characters, because five characters are needed when including the blank character (your 7-segment decoder will have to use 3-bit codes, and you will need to use 3-bit wide 6-to-1 multiplexers). You will need to use three select lines for each of the multiplexers: connect the select lines to switches SW₉₇. In your VHDL code connect constants to the 6-to-1 (or 8-to-1) multiplexers that select each character, because there are not enough SW switches.

SW97		Character pattern
000		d	E	1	0
001		d E	1	0
010	d	E 1	0
011	E	1 0			d
100	1	0		d	E
101	0		d	E	1

Table 4: Rotating the word dE10 on six displays.

Perform the following steps:

1. Create a new Quartus project for your circuit.
2. Connect the switches SW₉₇ to the select inputs of each instance of the multiplexers in your circuit. Connect constants in your VHDL code to the multiplexers as required to produce the patterns of characters shown in Table 4 or Table 5 depending on your DE-series board. Connect the outputs of your multiplexers to the 7-segment displays HEX5, ..., HEX0 of the DE10Lite, DE0-CV and DE1-SoC or HEX7, ..., HEX0 for the DE2-115.
3. Include the required pin assignments for your DE-series board for all switches, LEDs, and 7-segment displays. Compile the project.
4. Test the functionality of the circuit by toggling SW₉₇ to observe the rotation of the characters.

1. T₀ = A + B + c₀
2. if (T₀> 9) then
3. Z₀ = 10;
4. c₁ = 1;
5. else
6. Z₀ = 0;
7. c₁ = 0;
8. end if
9. S₀ = T₀ Z₀
10. S₁ = c₁

Can anyone help me solve this as I am running out of time?

This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversions and binary-coded-decimal (BCD) addition. Part I We wish to display on the 7-segment displays HEX1 and HEXO the values set by the switches SW7-0. Let the values denoted by SW 7-4 and SW3-o be displayed on HEX1 and HEXO, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as don't cares. 1. Create a new project which will be used to implement the desired circuit on your Intel FPGA DE-series board. The intent of this exercise is to manually derive the logic functions needed for the 7-segment displays. Therefore, you should use only simple VHDL assignment statements in your code and specify each logic function as a Boolean expression. 2. Write a VHDL file that provides the necessary functionality. Include this file in your project and assign the pins on the FPGA to connect to the switches and 7-segment displays. Make sure to include the necessary pin assignments. 3. Compile the project and download the compiled circuit into the FPGA chip. 4. Test the functionality of your design by toggling the switches and observing the displays. Part II You are to design a circuit that converts a four-bit binary number V = V3 U2U1Vinto its two-digit decimal equiv- alent D = dido. Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. It includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit. U3020100 di do 0 0000 0001 0010 0 0 1 0 2 0 1001 1010 1011 1100 1101 1110 1111 9 0 1 2 1 5 Table 1: Binary-to-decimal conversion values. The output 2 for the comparator circuit can be specified using a single Boolean expression, with the four inputs V3-0. Design this Boolean expression by making a truth table that shows the valuations of the inputs V3-0 for which has to be 1. di 0 Comparator Z >9 0 Circuit A Figure 1: Partial design of the binary-to-decimal conversion circuit. Notice that the circuit in Figure 1 includes a 4-bit wide 2-to-1 multiplexer (a similar multiplexer was described as part of Laboratory Exercise 1). The purpose of this multiplexer is to drive digit do with the value of V when 2 = 0, and the value of A when 2 = 1. To design circuit A consider the following. For the input values V 9, the multiplexer will select A. Thus, A has to provide output values that properly implement Table 1 when V > 9. You need to design circuit A so that the input V = 1010 gives an output A = 0000, the input V = 1011 gives the output A = 0001, ..., and the input V = 1111 gives the output A = 0101. Design circuit A by making a truth table with the inputs V3-0 and the outputs A3-0- Perform the following steps: 1. Write VHDL code to implement your design. The code should have the 4-bit input SW3-0, which should be used to provide the binary number V, and the two 7-bit outputs HEX1 and HEXO, to show the values of decimal digits di and do. The intent of this exercise is to use simple VHDL assignment statements to specify the required logic functions using Boolean expressions. Your VHDL code should not include any IF-ELSE, CASE, or similar statements. 2. Make a Quartus project for your VHDL entity. 3. Compile the circuit and use functional simulation to verify the correct operation of your comparator, multi- plexers, and circuit A. 4. Download the circuit into an FPGA board. Test the circuit by trying all possible values of V and observing the output displays. Part III Figure 2a shows a circuit for a full adder, which has the inputs a, b, and C, and produces the outputs s and Co. Parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sum cos = a +b+c. Figure 2d shows how four instances of this full adder module can be used to design a circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of the way that the carry signals are passed from one full adder to the next. Write VHDL code that implements this circuit, as described below. ci a Ci S FA PO b b Co a) Full adder circuit b) Full adder symbol baci COS bz az cz b2a2c2 b1 ai 61 bo do Cin 0 0 0 0 0 1 010 0 1 1 100 101 1 1 0 1 1 FA FA FA FA 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 Cout S3 S2 so c) Full adder truth table d) Four-bit ripple-carry adder circuit Figure 2: A ripple-carry adder circuit. 1. Create a new Quartus project for the adder circuit. Write a VHDL entity for the full adder subcircuit and write a top-level VHDL entity that instantiates four instances of this full adder. 2. Use switches SW7-4 and SW3-0 to represent the inputs A and B, respectively. Use SW, for the carry-in Cin of the adder. Connect the outputs of the adder, Cout and S, to the red lights LEDR. 3. Include the necessary pin assignments for your DE-series board, compile the circuit, and download it into the FPGA chip. 4. Test your circuit by trying different values for numbers A, B, and Cin. Part IV In Part II we discussed the conversion of binary numbers into decimal digits. For this part you are to design a circuit that has two decimal digits, X and Y, as inputs. Each decimal digit is represented as a 4-bit number. In technical literature this is referred to as the binary coded decimal (BCD) representation. You are to design a circuit that adds the two BCD digits. The inputs to your circuit are the numbers X and Y , plus a carry-in, Cin. When these inputs are added, the result will be a 5-bit binary number. But this result is to be displayed on 7-segment displays as a two-digit BCD sum SiSo. For a sum equal to zero you would display Siso = 00, for a sum of one S So = 01, for nine Siso = 09, for ten S1 So = 10, and so on. Note that the inputs X and Y are assumed to be decimal digits, which means that the largest sum that needs to be handled by this circuit is Siso = 9+9+1 = 19. Perform the steps given below. 1. Create a new Quartus project for your BCD adder. You should use the four-bit adder circuit from Part III to produce a four-bit sum and carry-out for the operation X +Y. A good way to work out the design of your circuit is to first make it handle only sums (X+Y) 9) then 3 Zo = 10; 4 C1 = 1; 5 else 6 Zo = 0; 7 Ci = 0; 8 end if 9 So = To - Zo 10 Si = C1 It is reasonably straightforward to see what circuit could be used to implement this pseudo-code. Lines 1 and 9 represent adders, lines 2-8 correspond to multiplexers, and testing for the condition To > 9 requires comparators. You are to write VHDL code that corresponds to this pseudo-code. Note that you can perform addition operations in your VHDL code instead of the subtraction shown in line 9. The intent of this part of the exercise is to examine the effects of relying more on the VHDL compiler to design the circuit by using IF-ELSE statements along with the VHDL > and + operators. Perform the following steps: 1. Create a new Quartus project for your VHDL code. Use switches SW7-4 and SW3-0 for the inputs A and B, respectively, and use SW, for the carry-in. The value of A should be displayed on the 7-segment display HEX5, while B should be on HEX3. Display the BCD sum, SiSo, on HEX1 and HEXO. 2. Use the Quartus RTL Viewer tool to examine the circuit produced by compiling your VHDL code. Compare the circuit to the one you designed in Part IV. 3. Download your circuit onto your DE-series board and test it by trying different values for numbers A and B. Part VI Design a combinational circuit that converts a 6-bit binary number into a 2-digit decimal number represented in the BCD form. Use switches SW5-0 to input the binary number and 7-segment displays HEX1 and HEXO to display the decimal number. Implement your circuit on the DE1-SoC board and demonstrate its functionality. LORD CO 01 Download DE10-Lite CD http://de 10-lite.terasic.com/cd RNT ** ter asic RIZ Designed Manufactured by Tera U5 2013 3D ZRNE R15 8389 24 C15 ICSP 2215 VES VELVE SETSTORE 51 C12'cil 043XVBY UPS JPE POWER GOO Occ3PO4 SDRAM VON PS cza DOR33 03027 CLO DE SP NOO'Onun Vacs O JO2 DE10-Lite KEYO R47 CS3 for Intel FPGA University Program R97 2914 17 KEY1 1 IN ge 141,07 R46R48 87040 0 0 0 HEX HEX LEDRS LEDR7 LEDRE DRS HEEF.7.2 0 0 0 1 1 0 0 1 0 1 This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversions and binary-coded-decimal (BCD) addition. Part I We wish to display on the 7-segment displays HEX1 and HEXO the values set by the switches SW7-0. Let the values denoted by SW 7-4 and SW3-o be displayed on HEX1 and HEXO, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as don't cares. 1. Create a new project which will be used to implement the desired circuit on your Intel FPGA DE-series board. The intent of this exercise is to manually derive the logic functions needed for the 7-segment displays. Therefore, you should use only simple VHDL assignment statements in your code and specify each logic function as a Boolean expression. 2. Write a VHDL file that provides the necessary functionality. Include this file in your project and assign the pins on the FPGA to connect to the switches and 7-segment displays. Make sure to include the necessary pin assignments. 3. Compile the project and download the compiled circuit into the FPGA chip. 4. Test the functionality of your design by toggling the switches and observing the displays. Part II You are to design a circuit that converts a four-bit binary number V = V3 U2U1Vinto its two-digit decimal equiv- alent D = dido. Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. It includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit. U3020100 di do 0 0000 0001 0010 0 0 1 0 2 0 1001 1010 1011 1100 1101 1110 1111 9 0 1 2 1 5 Table 1: Binary-to-decimal conversion values. The output 2 for the comparator circuit can be specified using a single Boolean expression, with the four inputs V3-0. Design this Boolean expression by making a truth table that shows the valuations of the inputs V3-0 for which has to be 1. di 0 Comparator Z >9 0 Circuit A Figure 1: Partial design of the binary-to-decimal conversion circuit. Notice that the circuit in Figure 1 includes a 4-bit wide 2-to-1 multiplexer (a similar multiplexer was described as part of Laboratory Exercise 1). The purpose of this multiplexer is to drive digit do with the value of V when 2 = 0, and the value of A when 2 = 1. To design circuit A consider the following. For the input values V 9, the multiplexer will select A. Thus, A has to provide output values that properly implement Table 1 when V > 9. You need to design circuit A so that the input V = 1010 gives an output A = 0000, the input V = 1011 gives the output A = 0001, ..., and the input V = 1111 gives the output A = 0101. Design circuit A by making a truth table with the inputs V3-0 and the outputs A3-0- Perform the following steps: 1. Write VHDL code to implement your design. The code should have the 4-bit input SW3-0, which should be used to provide the binary number V, and the two 7-bit outputs HEX1 and HEXO, to show the values of decimal digits di and do. The intent of this exercise is to use simple VHDL assignment statements to specify the required logic functions using Boolean expressions. Your VHDL code should not include any IF-ELSE, CASE, or similar statements. 2. Make a Quartus project for your VHDL entity. 3. Compile the circuit and use functional simulation to verify the correct operation of your comparator, multi- plexers, and circuit A. 4. Download the circuit into an FPGA board. Test the circuit by trying all possible values of V and observing the output displays. Part III Figure 2a shows a circuit for a full adder, which has the inputs a, b, and C, and produces the outputs s and Co. Parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sum cos = a +b+c. Figure 2d shows how four instances of this full adder module can be used to design a circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of the way that the carry signals are passed from one full adder to the next. Write VHDL code that implements this circuit, as described below. ci a Ci S FA PO b b Co a) Full adder circuit b) Full adder symbol baci COS bz az cz b2a2c2 b1 ai 61 bo do Cin 0 0 0 0 0 1 010 0 1 1 100 101 1 1 0 1 1 FA FA FA FA 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 Cout S3 S2 so c) Full adder truth table d) Four-bit ripple-carry adder circuit Figure 2: A ripple-carry adder circuit. 1. Create a new Quartus project for the adder circuit. Write a VHDL entity for the full adder subcircuit and write a top-level VHDL entity that instantiates four instances of this full adder. 2. Use switches SW7-4 and SW3-0 to represent the inputs A and B, respectively. Use SW, for the carry-in Cin of the adder. Connect the outputs of the adder, Cout and S, to the red lights LEDR. 3. Include the necessary pin assignments for your DE-series board, compile the circuit, and download it into the FPGA chip. 4. Test your circuit by trying different values for numbers A, B, and Cin. Part IV In Part II we discussed the conversion of binary numbers into decimal digits. For this part you are to design a circuit that has two decimal digits, X and Y, as inputs. Each decimal digit is represented as a 4-bit number. In technical literature this is referred to as the binary coded decimal (BCD) representation. You are to design a circuit that adds the two BCD digits. The inputs to your circuit are the numbers X and Y , plus a carry-in, Cin. When these inputs are added, the result will be a 5-bit binary number. But this result is to be displayed on 7-segment displays as a two-digit BCD sum SiSo. For a sum equal to zero you would display Siso = 00, for a sum of one S So = 01, for nine Siso = 09, for ten S1 So = 10, and so on. Note that the inputs X and Y are assumed to be decimal digits, which means that the largest sum that needs to be handled by this circuit is Siso = 9+9+1 = 19. Perform the steps given below. 1. Create a new Quartus project for your BCD adder. You should use the four-bit adder circuit from Part III to produce a four-bit sum and carry-out for the operation X +Y. A good way to work out the design of your circuit is to first make it handle only sums (X+Y) 9) then 3 Zo = 10; 4 C1 = 1; 5 else 6 Zo = 0; 7 Ci = 0; 8 end if 9 So = To - Zo 10 Si = C1 It is reasonably straightforward to see what circuit could be used to implement this pseudo-code. Lines 1 and 9 represent adders, lines 2-8 correspond to multiplexers, and testing for the condition To > 9 requires comparators. You are to write VHDL code that corresponds to this pseudo-code. Note that you can perform addition operations in your VHDL code instead of the subtraction shown in line 9. The intent of this part of the exercise is to examine the effects of relying more on the VHDL compiler to design the circuit by using IF-ELSE statements along with the VHDL > and + operators. Perform the following steps: 1. Create a new Quartus project for your VHDL code. Use switches SW7-4 and SW3-0 for the inputs A and B, respectively, and use SW, for the carry-in. The value of A should be displayed on the 7-segment display HEX5, while B should be on HEX3. Display the BCD sum, SiSo, on HEX1 and HEXO. 2. Use the Quartus RTL Viewer tool to examine the circuit produced by compiling your VHDL code. Compare the circuit to the one you designed in Part IV. 3. Download your circuit onto your DE-series board and test it by trying different values for numbers A and B. Part VI Design a combinational circuit that converts a 6-bit binary number into a 2-digit decimal number represented in the BCD form. Use switches SW5-0 to input the binary number and 7-segment displays HEX1 and HEXO to display the decimal number. Implement your circuit on the DE1-SoC board and demonstrate its functionality. LORD CO 01 Download DE10-Lite CD http://de 10-lite.terasic.com/cd RNT ** ter asic RIZ Designed Manufactured by Tera U5 2013 3D ZRNE R15 8389 24 C15 ICSP 2215 VES VELVE SETSTORE 51 C12'cil 043XVBY UPS JPE POWER GOO Occ3PO4 SDRAM VON PS cza DOR33 03027 CLO DE SP NOO'Onun Vacs O JO2 DE10-Lite KEYO R47 CS3 for Intel FPGA University Program R97 2914 17 KEY1 1 IN ge 141,07 R46R48 87040 0 0 0 HEX HEX LEDRS LEDR7 LEDRE DRS HEEF.7.2 0 0 0 1 1 0 0 1 0 1