FIFO, Write Back, Write on Allocate options.

SET THE VALUE OF Offset Bits $=0$ Set Cache $1=$ Direct Mapped Cache Set Cache $2=$ Fully Associative Cache Set Cache $3=2-$Way

Set Associative Cache Set Cache $4=4-$Way Set Associative Cache

CHANGE THE FOLLOWING PARAMETERS

Always set Memory Size $>$ size of Cache then press Submit Next press Gen. $88$ Random Instructions. Then press Submit.

To see how each instruction is loaded from memory or from Cache, depending upon availability, press Next Instruction.

Press Fast Forward to execute all $88$ instructions, one after the other.

TO OBSERVE AND REPORT

$1.$ For All caches $($Direct Mapping$)$

a$.$ Set the size of Cache so that Direct Mapping has the maximum hit ratio and minimum miss

ratio?

b$.$ How can you increase the hit ratio in case of direct mapping by changing some of size of

Caches?

c$.$ In presentation, show the pictures from the simulator containing the values used and results

obtained. Also, give reasons why the hit ratio increases when you change the size of

caches?

d$.$ Explain the reason for the number of bits being used for Tag and for the number of bits

required for RAM address?

$2.$ For All caches $($Fully Associative Mapping$)$

a$.$ Set the size of Cache so that Fully Associative Mapping has the maximum hit ratio and

minimum miss ratio?

b$.$ How can you increase the hit ratio in case of Fully Associative Mapping by changing some

of size of Caches?

c$.$ In presentation, show the pictures from the simulator containing the values used and results

obtained. Also, give reasons why the hit ratio increases when you change the size of

caches?

d$.$ Explain the reason for the number of bits being used for Tag and for the number of bits

required for RAM address?

$3.$ For All caches $(4-$way Associative Mapping$)$

a$.$ Set the size of Cache so that $4-$way Associative Mapping has the maximum hit ratio and

minimum miss ratio?

b$.$ How can you increase the hit ratio in case of $4-$way Associative Mapping by changing

some of size of Caches?

c$.$ In presentation, show the pictures from the simulator containing the values used and results

obtained. Also, give reasons why the hit ratio increases when you change the size of

caches?

d$.$ Explain the reason for the number of bits being used for Tag and for the number of bits

required for RAM address?