Figure 1 shows an architecture for a twos complementer based on this algorithm. It consists of an 8-bit shift register with parallel load capability, a counter, and a control unit. The control unit generates the 7 required control signals : D, Shift, Load, Inc, Clr, ld_done, and clr_done.

The algorithm begins by first loading a number into the 8-bit shift register and clearing the counter and done flipflop to 0. The least significant bit of the shift register is examined, and based upon its value the control unit then sets the D signal to the appropriate value and shifts it into the most significant position of the shift register. This process is repeated until all 8 bits of the original number have been examined. At this point, the shift register will contain the twos complement of the original number. A Done flip-flop is used to indicate that the algorithm is complete.

You are to design an ASM chart (Moore style) which implements this algorithm using the given datapath.

Implement the datapath and control unit using VHDL processes. Use the following entity specification:

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity twos_complementer is port(din : in std_logic_vector(7 downto 0); reset : in std_logic ; clk : in std_logic ; done_out : out std_logic ; counter_out : out std_logic_vector(3 downto 0); reg_out : out std_logic_vector(7 downto 0)); end twos_complementer ;

done D Q clr done ld done L Clk number to be loaded in bit 0 Asynchronous reset 8-bit shift registe Control Unit with load Shift Load Inc Clk Counter CIr Q A CIk Clk Figure 1: Serial two's complementer block diagram. done D Q clr done ld done L Clk number to be loaded in bit 0 Asynchronous reset 8-bit shift registe Control Unit with load Shift Load Inc Clk Counter CIr Q A CIk Clk Figure 1: Serial two's complementer block diagram