Figure 11.9 shows a multiplier for unsigned integers in (a) and for signed integers in (b), with WIDTH bits for the inputs and 2-WIDTH bits for the output. a) According to section 10.7, which are the right "arithmetic" types for implementing these circuits? Recall that, for the circuit ports, the default types are the standard-logic types. b) Complete the plot for prod in both figures. c) Implement both multipliers in the same VHDL code (call the outputs prod_uns and prod sig). Enter WIDTH as a generic parameter and observe notes 2 to 4 above. d) Show simulation results using the same stimuli of figure 11.9, with only binary values and 80ns for the smaller time slots. Compare then prod_uns and prod_sig to the results from part (b). e) Finally, using the same stimuli but only decimal (instead of binary) values for all signals, show a graph with the simulation results for figure 11.9a only (i.e., without the plot for prod_sig) and another graph for figure 11.9b only (without the prod_uns plot), then comment on the correctness of the results. 278 (a) a b 1000 prod 00111000 b. 0111 0110 Unsigned multiplier 1000 Figure 11.9 Multipliers of exercise 11.9. -prod 1000 1111 0111 (b) 1000 8- b- 0111 prod 11001000 0110 Signed multiplier 1000 Chapter 11 -prod 1000 1111 0111