figure 2.4

figure 2.1

Detail the stages of executing the MOV instructions of Figure 2.4, assuming an 8-bit processor and a 16-bit IR and program memory following the model of Figure 2.1. Example: the stages for the ADD instruction are (1) fetch M[PC] into IR, (2) read Rn and Rm from register file through ALU configured for ADD, storing results back in Rn. Figure 2.4: Pipelining: (a) non-pipelined dish cleaning, (b) pipelined dish cleaning, (c) pipelined instruction execution. Wash 1 2 3 4 5 6 7 8 Non-pipelined 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Pipelined 1 2 3 4 5 6 7 8 Dry + (a) Time (b) Time 6 Fetch-instr. Decode Fetch ops. Execute Store res. 1 2 3 4 5 78 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Pipelined 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 HHH (0) Time Figure 2.1: General-purpose processor basic architecture. Processor Controller Datapath Control /Status Next-state and control logic ALU PC IR Registers I/O Memory