Figure 4.23) PU a better overall design cise, we examine how pipelining affects the clock cycle time of the s in this exercise assume that individual stages of the datapath ro have the following latencies ID EX 150 ps IF MEM 350 ps WB 250ps 300 ps 200 ps s assume that instructions executed by the processor are broken down as follows: ALU/Logic 45% Jump/Branch 20% LDUR STUR 20% 15% 4.16.1 [5] What is the clock cycle time in a pipelined and non-pipelined processor? 4,16.2 [10] What is the total latency of an LDUR instruction in a pipelinesd and non-pipelined processor? [ 1 0] If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? -4.16.3 4.16.4 [10] Assuming there are no stalls or hazards, whatis the utilization of the data memory