Figure Q6 shows a functional block diagram of a custom processor and the Register Transfer Level (RTL) codes to perform one of the processor operations. Assume that signal p and q are never '1' simultaneously. The ALU operation is given in Table Q6. SO: ( ) /R12; S1: (p) /R2 R1; R1 R2 (p) /R2 R1; S2: (p) / R1 R1 + R2; (pq) /R20; S3: (p) /R2