Fill in the pipeline diagram below for the following code, assuming it is running on the pipelined machine with full forwarding support. Make sure to denote stalls and use arrows to show forwarding. You can refer to Fig 4.60 for the pipelined processor overview, with both the hazard detection unit and the forwarding unit. lw $t0, 0($s0) lw $t1, 0($t0) addi $t0, $t0, 4 addi $t1, $t1, 4 sw $t1, 0($s0) Fill in the pipeline diagram below for the code in (a), assuming a new pipelined machine (with full forwarding support). This new pipeline breaks MEM into two stages (presuming that was the bottleneck). So a memory operation (e.g., lw) will start memory access in Ml (still having calculated the address in EX) but does not complete the operation until the end of M2. Make sure to denote stalls and use arrows to show forwarding. If breaking the MEM stage into two as described in (b) reduces the cycle time from 260ns to 240ns. by how much did the performance of the code in (a) improve