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Fill out the ALL Outputs for the truth table of slice MSB and slice 0 of a 32 bits MIPS ALU, with explanation for slt

Fill out the ALL Outputs for the truth table of slice MSB and slice 0 of a 32 bits MIPS ALU, with explanation for slt and sltu operations.

Slice MSB PLA inputs PLA outputs
In8 In7 In6 In5 In4 In3 In2 In1 In0 Out3 Out2 Out1 Out0
Instruction func5 func4 func3 func2 func1 func0 A B C Ov TS slt R
add 1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1 0
1 0 0 0 0 0 0 1 1
1 0 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
1 0 0 0 0 0 1 1 0
1 0 0 0 0 0 1 1 1
addu 1 0 0 0 0 1 0 0 0
1 0 0 0 0 1 0 0 1
1 0 0 0 0 1 0 1 0
1 0 0 0 0 1 0 1 1
1 0 0 0 0 1 1 0 0
1 0 0 0 0 1 1 0 1
1 0 0 0 0 1 1 1 0
1 0 0 0 0 1 1 1 1
sub 1 0 0 0 1 0 0 0 0
1 0 0 0 1 0 0 0 1
1 0 0 0 1 0 0 1 0
1 0 0 0 1 0 0 1 1
1 0 0 0 1 0 1 0 0
1 0 0 0 1 0 1 0 1
1 0 0 0 1 0 1 1 0
1 0 0 0 1 0 1 1 1
subu 1 0 0 0 1 1 0 0 0
1 0 0 0 1 1 0 0 1
1 0 0 0 1 1 0 1 0
1 0 0 0 1 1 0 1 1
1 0 0 0 1 1 1 0 0
1 0 0 0 1 1 1 0 1
1 0 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1 1
and 1 0 0 1 0 0 0 0 0
1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 1 0
1 0 0 1 0 0 0 1 1
1 0 0 1 0 0 1 0 0
1 0 0 1 0 0 1 0 1
1 0 0 1 0 0 1 1 0
1 0 0 1 0 0 1 1 1
or 1 0 0 1 0 1 0 0 0
1 0 0 1 0 1 0 0 1
1 0 0 1 0 1 0 1 0
1 0 0 1 0 1 0 1 1
1 0 0 1 0 1 1 0 0
1 0 0 1 0 1 1 0 1
1 0 0 1 0 1 1 1 0
1 0 0 1 0 1 1 1 1
xor 1 0 0 1 1 0 0 0 0
1 0 0 1 1 0 0 0 1
1 0 0 1 1 0 0 1 0
1 0 0 1 1 0 0 1 1
1 0 0 1 1 0 1 0 0
1 0 0 1 1 0 1 0 1
1 0 0 1 1 0 1 1 0
1 0 0 1 1 0 1 1 1
nor 1 0 0 1 1 1 0 0 0
1 0 0 1 1 1 0 0 1
1 0 0 1 1 1 0 1 0
1 0 0 1 1 1 0 1 1
1 0 0 1 1 1 1 0 0
1 0 0 1 1 1 1 0 1
1 0 0 1 1 1 1 1 0
1 0 0 1 1 1 1 1 1
slt 1 0 1 0 1 0 0 0 0
1 0 1 0 1 0 0 0 1
1 0 1 0 1 0 0 1 0
1 0 1 0 1 0 0 1 1
1 0 1 0 1 0 1 0 0
1 0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 1 0
1 0 1 0 1 0 1 1 1
sltu 1 0 1 0 1 1 0 0 0
1 0 1 0 1 1 0 0 1
1 0 1 0 1 1 0 1 0
1 0 1 0 1 1 0 1 1
1 0 1 0 1 1 1 0 0
1 0 1 0 1 1 1 0 1
1 0 1 0 1 1 1 1 0
1 0 1 0 1 1 1 1 1
Slice 0 PLA Inputs PLA outputs
In8 In7 In6 In5 In4 In3 In2 In1 In0 Out2 Out1 Out0
Instruction func5 func4 func3 func2 func1 func0 A B slt TS Co R TS PLA terms
add 1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1 0
1 0 0 0 0 0 0 1 1
1 0 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 1
1 0 0 0 0 0 1 1 0
1 0 0 0 0 0 1 1 1
addu 1 0 0 0 0 1 0 0 0
1 0 0 0 0 1 0 0 1
1 0 0 0 0 1 0 1 0
1 0 0 0 0 1 0 1 1
1 0 0 0 0 1 1 0 0
1 0 0 0 0 1 1 0 1
1 0 0 0 0 1 1 1 0
1 0 0 0 0 1 1 1 1
sub 1 0 0 0 1 0 0 0 0
1 0 0 0 1 0 0 0 1
1 0 0 0 1 0 0 1 0
1 0 0 0 1 0 0 1 1
1 0 0 0 1 0 1 0 0
1 0 0 0 1 0 1 0 1
1 0 0 0 1 0 1 1 0
1 0 0 0 1 0 1 1 1
subu 1 0 0 0 1 1 0 0 0
1 0 0 0 1 1 0 0 1
1 0 0 0 1 1 0 1 0
1 0 0 0 1 1 0 1 1
1 0 0 0 1 1 1 0 0
1 0 0 0 1 1 1 0 1
1 0 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1 1
and 1 0 0 1 0 0 0 0 0
1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 1 0
1 0 0 1 0 0 0 1 1
1 0 0 1 0 0 1 0 0
1 0 0 1 0 0 1 0 1
1 0 0 1 0 0 1 1 0
1 0 0 1 0 0 1 1 1
or 1 0 0 1 0 1 0 0 0
1 0 0 1 0 1 0 0 1
1 0 0 1 0 1 0 1 0
1 0 0 1 0 1 0 1 1
1 0 0 1 0 1 1 0 0
1 0 0 1 0 1 1 0 1
1 0 0 1 0 1 1 1 0
1 0 0 1 0 1 1 1 1
xor 1 0 0 1 1 0 0 0 0
1 0 0 1 1 0 0 0 1
1 0 0 1 1 0 0 1 0
1 0 0 1 1 0 0 1 1
1 0 0 1 1 0 1 0 0
1 0 0 1 1 0 1 0 1
1 0 0 1 1 0 1 1 0
1 0 0 1 1 0 1 1 1
nor 1 0 0 1 1 1 0 0 0
1 0 0 1 1 1 0 0 1
1 0 0 1 1 1 0 1 0
1 0 0 1 1 1 0 1 1
1 0 0 1 1 1 1 0 0
1 0 0 1 1 1 1 0 1
1 0 0 1 1 1 1 1 0
1 0 0 1 1 1 1 1 1
slt 1 0 1 0 1 0 0 0 0
1 0 1 0 1 0 0 0 1
1 0 1 0 1 0 0 1 0
1 0 1 0 1 0 0 1 1
1 0 1 0 1 0 1 0 0
1 0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 1 0
1 0 1 0 1 0 1 1 1
sltu 1 0 1 0 1 1 0 0 0
1 0 1 0 1 1 0 0 1
1 0 1 0 1 1 0 1 0
1 0 1 0 1 1 0 1 1
1 0 1 0 1 1 1 0 0
1 0 1 0 1 1 1 0 1
1 0 1 0 1 1 1 1 0
1 0 1 0 1 1 1 1 1

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