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Fill the table below with the value of each expression as a Verilog numeric literal including the correct width and the correct value in hexadecimal

Fill the table below with the value of each expression as a Verilog numeric literal including the correct width and the correct value in hexadecimal base. Assume the following declarations:
logic [7:0]x
logic [3:0]y;
and that x has the value 8'hbb and that y has the value 4'b1100.
\table[[expression,value],[x[3:0],],[x[7:4]??y,],[{y,x[7:4]},],[
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