Fill the truth table of the given sequential logic circuit. Assume Q to be the value of the output after the corresponding logic gates have been given enough time to produce the output according to the inputs. If you feel the older Q value will be preserved by the input combination, put "Latch" in the table for the output Q. (6 ponots) WE Forbiddein A pair of positive edge-triggered (i.e. rising edge triggered) D-flip-flops are connected as shown below. Complete the timing diagram below for this cireuit. Ignore propagation delays. Assume, initially. (6 points) CLK CLK 0 Q1 0 0 0